The present invention is generally directed to the fabrication of field effect transistor (FET) devices. More particularly, the present invention is directed to a method for the fabrication of an inlay transistor with self-aligned source and drain and metallization areas. Additionally, the process of the present invention is amenable to fabrication of lightly doped drain and/or source regions to reduce problems associated with electric high fields in the transistor channel region.
As integrated circuit dimensions have shrunk, the supply voltages supplied to various chip devices have not been correspondingly scaled. The primary reason for this failure to scale is the inconvenience of providing power supply voltages at a multitude of distinct levels. Compatibility with existing systems and integrated circuit boards is also a factor. This situation, namely the shrinking of device dimensions together with the lack of reduction in supply voltage, naturally leads to situations in which high electric fields are present, particularly in the channel region of field effect transistor devices. Accordingly, it is desirable to provide source and drain region profiles which mitigate the high electric field problem. Lightly doped source and drain region extensions provide one mechanism for mitigating this problem.
Very large scale integrated circuit (VLSI) fabrication methods employ masks through which photoresist materials are exposed, developed, and selectively removed. The larger the number of electrical and electronic components that are disposed on such circuit chips, the greater is the problem of mask registration and alignment. That is to say, masking processes after the first must provide proper alignment with the patterns that have previously been disposed on the semiconductor substrate. It is accordingly seen then that it is generally desirable to employ fewer masking steps whenever possible. This is particularly true for the purpose of avoiding registration errors from the one masking pattern to the next. However, as dimensions shrink, alignment becomes more difficult.
It is therefore seen that the problem of high field strength together with mask registration each act to limit the dimensions to which integrated circuits can be shrunk. Each of these problems are, however, mitigated by the process of the present invention in which self-aligned structures are employed which do not require masking operations for their formation.